Portfolios - Page 6 of 7

Biss-C Receiver

BiSS is an open-source digital interface for sensors and actuators introduced by iC-Haus GmbH in 2002. BiSS stands for bidirectional serial synchronous — it is a high speed serial synchronous bi-directional full-duplex communication protocol compliant with RS-422/485 standards. BiSS-C mode is the continuous mode in which the BiSS-C receiver reads out the position data cyclically.

CouthIT’s BiSS-C receiver implementation interfaces with BiSS-C encoders connected in point-to-point or in daisy-chain/bus topology. BiSS-C encoders provide high resolution absolute single turn and multi-turn position data along with status information. The BiSS protocol is used on the lower sensor/actuator communication level in industrial applications (e.g. motor feedback, robotics) which require high-speed data transfer rates, safety, flexibility and a minimized implementation effort. BiSS can address internal registers (via Control Communication) in the encoder that can be read by and written to by the BiSS-C Receiver with data about the encoder itself (identification, device data, resolution, etc.). The interface enables a complete closed-loop position control system by providing the real-time position feedback to the master to control the motor.

CouthIT’s BiSS-C receiver implementation has support for BiSS Safety profile as well. BiSS-C safety profile has been certified by TÜV Rheinland for safety-critical applications up to SIL3 according to IEC61508:2010. BiSS Safety uses the concept of a “Black Channel” transmission and specifies the data channel contents in order to ensure failure mode detection as defined in IEC61784-3 using redundant position words, different CRC polynomials and a sign-of-life counter. BiSS Safety is fully compatible with BiSS and all of its features including line delay compensation, processing times and daisy chaining of additional sensors.

Support for point-to-point and bus/daisy-chain communication.
Support for baud rates from 1 MHz, 2 MHz, 5 MHz, and 10 MHz.
Support for point to point and maximum of 3 encoders connected in daisy-chain.
Support for control communication for Register read and write access.
Support for processing delay compensation and line delay compensation.
Support for concurrent multi-channel support on a single PRU (up-to 3 channels with identical number of encoders of same frequency connected to all configured channels).
Support for multi-channel with different number of encoders connected across channels under load share model (this feature is specific to TI ICSSG wherein each of PRU, RTU-PRU, and TX-PRU from one PRU-ICSSG slice handles all 3 channels).
Support for Time triggered/Contineous mode cycle trigger operation.
Support for BiSS safety profile.
Support for 100 meter cable lengths depends on baud rate.
Support for 6-bit CRC for position data, 4-bit CRC for control communication data and 16-bit CRC in case of Safety profile.

Tested using 12-bit iC-Haus encoders, Wachendorff encoder, and 46-bit (single + multi turn) Higen encoders.
Tested for baud rates 1 Mhz, 2 MHz, 4 MHz, and 10 MHz.
Tested for absolute position data requests and register read and write using control communications.
Validated for safety and reliability with CRC checks as specified by the Standard.
Tested with 1 encoder connected in a point-to-point communication setup.
Tested with 3 encoders connected in a daisy-chain configuration.
Tested with up to 3 encoders connected in a bus.
Tested for multi-channel communication modes by simultaneously connected encoders to different PRUs in the ICSS.

TI AM243x, TI AM64x, TI AM263x and TI AM437x

Noise Suppression

CouthIT’s noise suppression module enhances the speech signal by suppressing stationary and non-stationary background noises and other perceivable distortions with minimal degradation in the speech quality. It operates on 16-bit PCM speech signals obtained from a single microphone, sampled at 8 khz or 16 khz, and generates an output speech signal with improved SNR and speech intelligibility. The algorithm can handle various dynamic noise environments (such as multi talker babble, car, street etc.) irrespective of variations in noise types or noise levels. The noise suppression module can be used in wireless and VoIP applications, digital hearing aids, tele-conferencing systems, speaker verification and speech recognition applications.

Based on the Spectral Subtraction algorithm.
Fixed-point ANSI C implementation.
Re-entrant implementation
C-callable APIs
Operates on 16-bit PCM speech signals sampled at 8 khz (narrow-band) or 16 khz (wide-band).
Uses a high performance internal voice activity detector (VAD).
Noise update is independent of VAD output.
Lookahead delay is 5 ms for narrow-band mode and 10 ms for wide-band mode.
Identifies and suppresses all types of stationary and non-stationary noises as well as mixed noise conditions.
Fast convergence and adaptation times for non-stationary noises (0.4 – 0.6 sec).
Provides better objective evaluation scores when compared to EVRC and Speex noise suppression algorithms.
Does not introduce any degradation in case of clean input speech samples.
Optimized for low memory foot print and low complexity.

Tested using a large database of narrow band and wide band speech and noise test vectors.
Tested using babble, car, street, and a combination of stationary and non-stationary background noises.
Tested using different speech and noise levels.
Performance benchmarked using objective evaluation measures such as segmental SNR, Log Likelihood Ratio, and Weighted Spectral Slope.
Tested for graceful exit in case of errors or exception.
Module is fully interruptible.
ARM implementation tested for any illegal memory access.
Tested for compliance with register preservation requirements
Tested for Input buffer corruption
Tested for I/O buffer alignment requirements
Tested for multi-instance implementation.
Tested with scratch contamination at frame boundaries
Tested for 100% code coverage
Range validation of all API parameters.
ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467/OMAPL138 (ARM926EJ-S) platforms.

ARM9E, ARM11, Cortex-A8, and Cortex-A9

Automatic Gain Control (AGC)

CouthIT’s Automatic Gain Control (AGC) module scales the speech signals to a specified value regardless of the variations in the input level in various dynamic environments such as car, multi talker babble, street etc. The AGC algorithm adaptively maintains the dynamic range of a speech signal without amplifying the non speech portions. This module can be used in wireless and VoIP applications, speaker phones, digital hearing aids, tele-conferencing systems, speaker verification and in speech recognition applications.

Fixed-point ANSI C implementation.
Re-entrant implementation.
C-callable APIs
Operates on 16-bit PCM speech signals sampled at 8 Khz (narrow-band) or 16 Khz (wide-band).
Provides a maximum gain of up to +20dBov and a minimum gain of -20dBov.
Provides protection against saturation or clipping of the signal.
User selectable desired output level.
User selectable response time.
Protection against excessive gain increase in case of background noise.
Protection for gain adjustment in case of low level speech portions with hangover period of 200 ms.
No amplification in case of silence intervals.
Optimized for low memory foot print and low complexity.

Tested using a large database of narrow band and wide band speech and noise test vectors.
Tested using babble, car, street, and a combination of stationary and non-stationary background noises.
Tested for different speech levels from -15dBov to -40dBov.
Tested in conjunction with CouthIT’s noise suppression module.
Tested for graceful exit in case of errors or exception.
Module is fully interruptible.
Tested for Input buffer corruption
Tested for I/O buffer alignment requirements
Tested for multi-instance implementation.
Tested with scratch contamination at frame boundaries
Tested for 100% code coverage
Range validation of all API parameters.
Code validated on Spectrum Digital C6455 DSK platform.
Code validated on OMAPL138 Platform.

ARM9E, ARM11, Cortex-A8, Cortex-A9, and TI C64x+.

H264 BP Decoder

H264 is a widely accepted video coding standard that was jointly developed by Video Coding Experts Group (VCEG) of the ITU-T and the Moving Picture Experts Group (MPEG) of ISO/IEC. It uses state-of-the-art coding tools and provides enhanced coding efficiency for a wide range of applications, including video telephony, video conferencing, TV, storage, streaming video and many others. H.264 standard defines several profiles and levels that specify restrictions on the bit stream and hence limits the capabilities needed to decode the bit streams. The Baseline Profile supports intra and inter-coding (using I-slices and P-slices) and entropy coding with context-adaptive variable-length codes (CAVLC). Potential applications of the Baseline Profile include video telephony, videoconferencing, streaming, and wireless communications.

Based on the ISO/IEC 14496-10 standard
Optimized ASM/C implementation.
Re-entrant implementation
C-callable APIs
Up to level 3 features of baseline profile supported.
Progressive frame type picture decoding supported.
Multiple slices and multiple reference frames supported.
CAVLC decoding supported
Intra-prediction and inter-prediction modes supported.
Block sizes of 4×4 supported.
Supports ASO and FMO features.
Frame cropping supported
Frame width of the range of 32 to 720 pixels supported.
Byte-stream syntax for the input bit stream supported.
Parsing of Supplemental Enhancement Information (SEI) and Video Usability Information (VUI)supported.
Long term reference frame and adaptive reference picture marking supported.
Gaps in the frame number supported.
Skipping of non reference pictures supported
Configurable delay for display of frames supported.
Outputs are available in YUV 420 planar formats.
Optional support for xDM 1.0 IVIDDEC2 APIs.

Implementation is tested for all JVT test streams
Implementation is tested for wide range of non-standard test vectors for all levels
Tested with error streams. Corrupted streams includes NAL, slice, MB level data & header corruptions.
Tested with 3gpp error pattern corrupted streams.
Tested for resource usage.(DMA channels, params etc)
Tested for illegal memory access by the module.
Module is fully interruptible.
Tested for compliance with register preservation requirements
Tested for Input buffer corruption
Tested for I/O buffer alignment requirements
Tested for multi-instance implementation.
Tested with scratch contamination at frame boundaries
Tested for 100% code coverage
Range validation of all API parameters.
Validated on einfochips C6472 EVM.

TI C64x+ and TI C66x

VP8 Codec

VP8 is an open source, royalty-free, video codec standardized by Internet Engineering Task Force (IETF), as RFC 6386, in the year 2011. It has been made available by Google under BSD license and is the default video codec in the Google WebRTC application. The codec operates on 8-bit YUV 420 progressive scans with resolutions up to 4K. The Encoder has an inhenrent support for multi-core implementation (up to 8 cores) and has an in-loop deblocking filter. The encoding complexity can be controlled using the cpu-use parameter which provides a lot of flexibility for real-time applications. The Decoder supports packet loss concealment. VP8 codec can be used in a wide range of applications such as video-conferencing, streaming, and storage applications.

Based on standard version VP8 1.1.0.
Optimized ASM/C implementation.
Re-entrant implementation
C-callable APIs
Frame width in the range of 16 to 720 pixels supported.
Frame height in the range of 16 to 1280 pixels supported.
Support for generation of Key Frame on demand.
Support for configuring the Key Frame interval at init-time.
Support for all the profiles defined in the standard.
Support for following settings for cpu_used: 5, 7, 9, and 15 (Encoder).
Support for up to 3-core implementation (Encoder).
Support for CBR and VBR mode of operation.
Support for the inherent packet loss concealment algorithm.
IVIDENC2/IVIDDEC2 interface standard complaint.

Implementation is tested for bit-compliance with the VP8 version 1.1.0.
Implementation is tested for wide range of non-standard test vectors for all resolutions.
Tested with error streams.
Tested with 3gpp error pattern corrupted streams.
Tested for resource usage (DMA channels, params etc)
Tested for illegal memory access by the module.
Module is fully interruptible.
Tested for compliance with register preservation requirements
Tested for Input buffer corruption
Tested for I/O buffer alignment requirements
Tested for multi-instance implementation.
Tested for multi-core implementation.
Tested with scratch contamination at frame boundaries
Tested for 100% code coverage
Range validation of all API parameters
Validated on TI C6678 EVM.

TI C66x

MP3 Encoder

MPEG-1 Layer 3 or MP3 was standardized by ISO/IEC in 1993. The standard operates on 16-bit mono or 2-channel (stereo) audio signals sampled at 32khz, 44.1khz, or 48khz and generates compressed bit-streams having bit-rates ranging from 32 kbps to 320 kbps per channel. The MPEG-2 Layer 3, standardized in 1995, extended the algorithm to support lower sampling frequencies (16 khz, 22.05khz, 24 khz) and additional bit-rates ranging from 8 kbps to 160 kbps. Psychoacoustic model, Modified Discrete Cosine Transform (MDCT) and Huffman coding play a vital role in achieving high compression ratios. MP3 is the most popular audio codec used in the industry today and has been extensively deployed in portable media players, mobile phones, as well as network connected devices.

Based on the ISO/IEC 11172-3 and ISO/IEC 13818-3 standards
Optimized C implementation.
Re-entrant implementation
C-callable APIs
Supports sampling frequencies 8, 11.025,12,16, 22.05, 24, 32, 44.1 and 48KHz respectively.
Supports for MPEG 2.5 Encoding.
Supports bit-rates ranging from 8 kbps to 320 kbps.
Support for mono and 2-channel stereo input.
Support for optional downmixing from stereo to mono.
Support for MS stereo option.
Optional support for xDM APIs.

Implementation tested for audio quality for a wide range of standard and non-standard test vectors.
Evaluated objective audio quality based on ITU BS.1387 standard.
Listening tests performed to ensure that no artifacts are present in encoded output
Tested for graceful exit in case of errors or exception.
Tested for illegal memory access by the module on ARM platform.
Tested for compliance with register preservation requirements
Module is fully interruptible.
Tested for Input buffer corruption
Tested for I/O buffer alignment requirements
Tested for multi-instance implementation.
Tested with scratch contamination at frame boundaries
Tested for 100% code coverage
Range validation of all API parameters.
ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.

ARM9E, ARM11, Cortex-A8, and Cortex-A9

IMA-ADPCM

IMA ADPCM is a 4-bit Adaptive Differential Pulse Code Modulation (ADPCM) algorithm standardized by the Interactive Multimedia Association (IMA). The codec operates on each 16-bit audio sample and generates a 4-bit ADPCM sample. The ADPCM algorithm is a waveform coding technique which predicts the current signal value from the previous values and transmits only the difference between the real and predicted value. The codec is widely deployed in Windows and Macintosh operating systems.

Based on IMA ADPCM open standard.
Fixed-point ANSI C implementation.
Re-entrant implementation
C-callable APIs
Operates on 16-bit input audio signals sampled at 8, 11.025, 22.05, or 44.1 KHz.
Bit-compliant with Microsoft Sound Recorder Application.
Support for mono and stereo channel modes.
Optional support for xDM APIs
Validated on TI DM6446 EVM platform.

Tested for compliance using a large database of audio test vectors
Tested for multi-instance implementation
Tested for various input block sizes
Tested for mono and stereo test vectors.
Tested for graceful exit in case of bit-stream related errors or exception.
Tested with scratch contamination at frame boundaries.
Range validation for all API parameters.
Tested for 100% code-coverage

ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C55x, and TI C64x+.

MS-RTA

Microsoft’s Real-time audio (MS-RTA) codec was introduced in 2006. MS-RTA is Microsoft’s proprietary audio codec and is subject to terms and conditions of Microsoft License agreement. It operates on 16-bit speech signals sampled at 8 KHz or 16 KHz and generates a compressed bit-stream having average bit-rates of 8.8 or 18 kbps respectively. It is a sub-band coder and has a look ahead delay of 10ms. The encoder optionally includes forward error correction (FEC) block to embed error recovery data in the bit-stream. The decoder has an optional jitter-control module that provides active management of jitter control and packet loss concealment. It is the default codec for Microsoft’s Unified Communications Platforms, and is designed for real-time, two way VoIP applications.

Based on Microsoft Standard specification
Optimized ASM/C implementation
Re-entrant implementation
C-callable APIs
Support for 8.8 kbps and 18 kbps average bit-rates.
Support for variable and fixed rate decoding.
Supports integrated Packet Loss Concealment (PLC) algorithm.
Support for direct-mode and pull-mode operation.
The implementation supports both Little-Endian and Big-Endian (on ARM and C64x+ platforms)
Optional support for xDM APIs.

Tested for bit-exactness with standard as well as a large database of non-standard test vectors
Module is fully interruptible (Maximum interrupt latency on C64x+ is 6000 cycles).
Tested for any illegal memory access by the module (C64x+ and ARM)
Tested for compliance with register preservation requirements
Tested for Input buffer corruption
Tested for I/O buffer alignment requirements
Tested for multi-instance implementation
Tested for 100% code coverage
Range validation for all the API parameters
Tested with scratch contamination at frame boundaries
Tested for packet loss conditions with 5% loss to 25% loss
Tested pull-mode decoder by simulating a large set of jitter conditions.
ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
TI C64x+ implementation validated on Spectrum Digital C6455 DSK, DM6446 EVM and OMAP3530 platform.
TI C55x implementation validated on Spectrum Digital C5510 DSK

ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C55x, and TI C64x+

OPUS

OPUS codec was standardized through RFC 6716 in 2012. It was designed for interactive speech and music transmission over Internet as well as for storage and streaming applications. The codec operates on variable frame lengths (2.5ms, 5ms, 10ms, 20ms, 40ms, and 60ms) of mono or stereo 16-bit PCM speech/audio signals sampled at 8 KHz, 12 KHz, 16 KHz, 24 KHz, or 48 KHz and generates a compressed bit-stream having bit-rates in the range of 6 kbps to 510 kbps respectively. It is based Skype’s SILK codec and Xiph.org’s CELT codec and supports Constant Bit Rate (CBR), Variable Bit Rate (VBR), and a constrained VBR mode. Opus Encoder provides an option to trade-off between complexity and quality, supports discontinuous transmission (DTX), and also supports Forward Error Correction (FEC), which increases the robustness against the packet losses. Opus Decoder supports packet loss concealment. OPUS codec can handle wide range of applications like Voice over IP (VoIP), video conferencing, in-game chat, remote live music perforamances. Opus support is mandatory in Google’s WebRTC framework.

Based on OPUS open-source standard version 1.3.1 (TI) and version 1.3 (Intel)
Fixed-point ANSI C implementation on TI platform.
Floating-point ANSI C implementation on AMD/Intel platform.
Re-entrant implementation
C-callable APIs
Operates on variable frame length (2.5ms, 5ms, 10ms, 20ms, 40ms, and 60ms)
Operates on speech/audio signals sampled at 8 Khz (NB), 12 Khz (MB), 16KHz (WB), 24KHz (SWB), and 48 Khz (FB)
Supports bit-rates ranging from 6 kbps to 510 kbps.
Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR) and constrained VBR.
Supports mono and stereo (2) channels. Supports to force the number of channels at both Encoder input and Decoder output.
Supports configuring the complexity level (ranges from 0 to 10) at init-time.
Supports configuring the bit-rate at run-time
Supports Forward Error Correction (FEC) for good robustness.
Optional support for xDM APIs.

Tested for bit-exactness with standard as well as a large database of non-standard test vectors.
Module is fully interruptible.
C64x+/C66x implementations tested for any illegal memory access.
Tested for compliance with register preservation requirements
Tested for Input buffer corruption
Tested for I/O buffer alignment requirements
Tested for multi-instance implementation
Tested for 100% code coverage
Range validation for all the API parameters
Tested with scratch contamination at frame boundaries
Tested for packet loss conditions with 5% loss to 25% loss
C64x+ implementation validated on C6472EVM platform.
C66x implementation validated on C6678EVM platform.
AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.

TI C66x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.

AMR-NB

Adaptive multi-rate – narrow band (AMR-NB) speech codec was adopted by the 3GPP for mobile telephony in 1998. The codec operates on each 20 ms frame of speech signals sampled at 8 KHz and generates compressed bit-streams with bit-rates ranging from 4.75 kbps to 12.2 kbps. The bit-rate can be changed at 20 ms frame boundary. The codec uses algebraic code excited linear prediction (ACELP) technique to compress speech at all bit rates. The codec provides voice activity detection (VAD) and comfort noise generation (CNG) algorithms for reduction in bit rate, and an inherent packet loss concealment (PLC) algorithm for handling frame erasures. The codec was primarily developed for mobile telephony over GSM and UMTS networks.

Based on 3GPP specification
Optimized ASM/C implementation
Re-entrant implementation
C-callable APIs
Operates on speech signal sampled at 8 KHz
Support for AMR bit rates 12.2, 10.2, 7.95, 7.40, 6.70, 5.90, 5.15, and 4.75 kbps respectively.
Support for EFR 12.2 kbps bit-rate.
The bitrate can be configured at 20ms frame boundary.
Support for RAW, IF1, IF2, and RFC bit-stream formats.
Supports integrated Packet Loss Concealment (PLC) algorithm.
The codec supports integrated Voice Activity Detection (VAD1 and VAD2) algorithm configurable at init-time.
Optional support for xDM APIs on TI platforms
The implementation supports both Little-Endian and Big-Endian on ARM and C64x+ platforms

Tested for bit exactness with the standard as well as large database of non-standard test vectors.
Module is fully interruptible. Maximum interrupt latency on C64x+ is 6000 cycles.
Tested for any illegal memory access by the module.
Tested for compliance with register preservation requirements.
Tested for Input buffer corruption.
Tested for I/O buffer alignment requirements.
Tested for multi-instance implementation.
Tested for 100% code coverage.
Range validation for all the API parameters.
Tested for Packet loss conditions with 5% loss to 25% loss.
ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
TI C64x implementation validated on Spectrum Digital C6416 DSK.
TI C64x+ implementation validated on Spectrum Digital C6455 DSK.
TI C55x implementation validated on Spectrum Digital C5510 DSK.
Cortex-M4 implementation validated on the TI Tiva TM4C1294 EVM.
AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.

ARM9E, ARM11, Cortex-M4, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.

BISS-C Receiver

CODEC OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

NOISE SUPPRESSION

MODULE OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

Automatic Gain Control (AGC)

MODULE OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

H264 BP DECODER

CODEC OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

VP8 Codec

CODEC OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

MP3 ENCODER

CODEC OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

IMA-ADPCM

CODEC OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

MS-RTA, Microsoft Real-Time Audio

CODEC OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

OPUS

CODEC OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details

AMR-NB

CODEC OVERVIEW

SALIENT FEATURES

TESTING FEATURES

AVAILABLE PLATFORM(S)

For datasheet with resource usage details