EVRC-NW

EVRC-NW

CODEC OVERVIEW

Enhanced Variable Rate Codec Narrowband-Wideband (EVRC-NW or Service Option 73 [SO 73]) was standardized by 3GPP2 in 2010. The EVRC-NW codec operates on each 20 ms frame of 16-bit speech signals sampled at 8 or16 KHz and generates compressed bit-stream of 171, 80, 40, or 16 bits respectively. This codec is an extension of both EVRC-B and EVRC-WB speech codecs and provides enhanced voice quality than EVRC-B and high spectral efficiency than EVRC-WB. It supports 8 different operating modes. EVRC-NW is interoperable with all modes of EVRC-WB and modes 0, 2 – 7 of EVRC-B. The codec supports mode change at frame boundaries and also contains a generic audio coding mode that can be used for handling non-speech signals such as music-on-hold and ring back tones. The principal applications of this codec are IP telephony, wideband telephony, video-telephony, gaming, streaming, ring back tones, media gateways and voice messaging servers.

SALIENT FEATURES
  • Based on 3GPP2 specification.
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 or 16 KHz.
  • Support for switching the anchor operating mode during run time.
  • Support for 7.5, 8.3, 6.64, 6.18, 5.82, 5.45, 5.08, and 4.0 kbps average source encoding bit-rates.
  • The maximum and minimum bit-rates can be configured during initialization.
  • The noise suppression module can be configured during initialization.
  • Support for dim and burst, eighth rate hangover, and null traffic frame features specified in the standard.
  • Support for RTP payload format as specified in the Internet Draft draft-ietf-avt-rtp-evrc-nw-01”.
  • Support for DTMF and TTY/TDD signals as specified in the standard.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for post-filter operation, configurable at frame boundary.
  • Supports integrated DTX mode of operation.
  • Support for choosing Motorola DTX/QualComm DTX at compile time.
  • Support for encoding music signals.
  • Support for decoding music signals.
  • Support for setting the minimum and maximum DTX update interval during initialization
  • Optional support for xDM APIs.
TESTING FEATURES
  • Tested for bit-exactness with standard as well as a large database of non-standard test vectors (TI).
  • Module is fully interruptible.
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested with scratch contamination at frame boundaries.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK, DM6467, DM6446, and OMAP3530 platforms.
  • AMD/Intel floating-point optimized implementation validated on Intel cores supporting SSE4 and above.
AVAILABLE PLATFORM(S)

TI C55x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.

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EVRC-B

EVRC-B

CODEC OVERVIEW

Enhanced Variable Rate Codec  B (EVRC-B) was standardized by 3GPP2 in 2006. The EVRC codec operates on each 20ms frame of 16-bit speech signals sampled at 8 KHz and generates compressed bit-streams with bit-rates of 8.3, 7.57, 6.64, 6.18, 5.82, 5.45, 5.08, and 4.0 kbps (source encoding rates) respectively. EVRC-B is based on the Code Excited Linear Prediction (CELP), Prototype Pitch Period (PPP), and Noise Excited Linear Prediction (NELP) coding algorithms. It  makes greater use of the intermediate coding rates through increased awareness of the nature of the individual speech samples. This more sophisticated coding approach allows EVRC-B to offer a voice quality equivalent to EVRC-A (IS-127), but at significantly lower average coding bit rates. The codec was primarily developed to replace the existing EVRC-A codec used in CDMA networks.

SALIENT FEATURES
  • Based on 3GPP2 specification.
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz.
  • Support for selecting anchor operating mode or average rate mode during initialization time
  • Support for 8.3, 7.57, 6.64, 6.18, 5.82, 5.45, 5.08, and 4.0 kbps source encoding bit-rates.
  • The maximum and minimum bit-rates can be configured during initialization.
  • The noise suppression module can be configured during initialization.
  • Support for dim and burst, eighth rate hangover, and null traffic frame features specified in the standard.
  • Support for RTP payload format as specified in RFC 4788.
  • Support for DTMF and TTY/TDD signals as specified in the standard.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for post-filter operation, configurable at frame boundary.
  • Supports integrated DTX mode of operation.
  • Support for setting the minimum and maximum DTX update interval during initialization
  • Little- and big-endian implementation on ARM and C6xx
  • Optional support for xDM APIs.
TESTING FEATURES
  • Tested for bit-exactness with standard as well as a large database of non-standard test vectors (TI/ARM).
  • Module is fully interruptible.
  • ARM and C6xx implementation tested for any illegal memory access.
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested with scratch contamination at frame boundaries.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • TI C64x implementation validated on Spectrum Digital C6416 DSK.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK, DM6467, DM6446, and OMAP3530 platforms.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • AMD/Intel optimized floating-point implementation validated on Intel cores supporting SSE4 and above.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.

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EVRC-A

EVRC-A

CODEC OVERVIEW

Enhanced Variable Rate Codec (EVRC-A) was standardized as IS-127 in 1995. The EVRC codec operates on each 20ms frame of 16-bit speech signals sampled at 8 KHz and generates compressed bit-streams with bit-rates of 9.6 kbps (full-rate), 4.8 kbps (half-rate), or 1.2 kbps (one-eighth rate) respectively. It is based on Relaxed Code Excited Linear Prediction (RCELP) algorithm. The codec chooses the bitrate based on the analysis of the input speech and the current operating mode (either normal or one of the reduced rate modes). It includes an adaptive noise suppressor to handle background noise and is robust under frame erasures and channel errors. The codec was primarily developed for use in CDMA networks.

SALIENT FEATURES
  • Based on IS-127/3GPP2 specification.
  • Optimized ASM/C implementation
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz.
  • Support for 9.6 kbps, 4.8 kbps, and 1.2 kbps bitrates.
  • The maximum and minimum bitrates can be configured during initialization.
  • The noise suppression module can be configured during initialization.
  • Support for RTP payload format as specified in RFC 3558.
  • Support for TTY/TDD signals as specified in the standard.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for post-filter operation, configurable at frame boundary.
  • Supports integrated DTX mode of operation.
  • Optional support for decoding of 3g2 streams.
  • Optional support for xDM APIs on TI platforms.
  • Little- and big-endian implementation on ARM.
TESTING FEATURES
  • Bit-exact with the standard test vectors (TI/ARM).
  • Module is fully interruptible.
  • ARM implementation tested for any illegal memory access.
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • AMD/Intel optimized floating-point implementation validated on Intel cores supporting SSE4 and above.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.

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EVRC-A

CODEC OVERVIEW

Enhanced Variable Rate Codec (EVRC-A) was standardized as IS-127 in 1995. The EVRC codec operates on each 20ms frame of 16-bit speech signals sampled at 8 KHz and generates compressed bit-streams with bit-rates of 9.6 kbps (full-rate), 4.8 kbps (half-rate), or 1.2 kbps (one-eighth rate) respectively. It is based on Relaxed Code Excited Linear Prediction (RCELP) algorithm. The codec chooses the bitrate based on the analysis of the input speech and the current operating mode (either normal or one of the reduced rate modes). It includes an adaptive noise suppressor to handle background noise and is robust under frame erasures and channel errors. The codec was primarily developed for use in CDMA networks.

SALIENT FEATURES
  • Based on IS-127/3GPP2 specification.
  • Optimized ASM/C implementation
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz.
  • Support for 9.6 kbps, 4.8 kbps, and 1.2 kbps bitrates.
  • The maximum and minimum bitrates can be configured during initialization.
  • The noise suppression module can be configured during initialization.
  • Support for RTP payload format as specified in RFC 3558.
  • Support for TTY/TDD signals as specified in the standard.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for post-filter operation, configurable at frame boundary.
  • Supports integrated DTX mode of operation.
  • Optional support for decoding of 3g2 streams.
  • Optional support for xDM APIs on TI platforms.
  • Little- and big-endian implementation on ARM.
TESTING FEATURES
  • Bit-exact with the standard test vectors (TI/ARM).
  • Module is fully interruptible.
  • ARM implementation tested for any illegal memory access.
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • AMD/Intel optimized floating-point implementation validated on Intel cores supporting SSE4 and above.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.

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EAAC+ Encoder

EAAC+ ENCODER

CODEC OVERVIEW

High Efficiency Advanced Audio Coding version 2 (HE-AAC v2) was standardized by MPEG and 3GPP in 2004. It is an extension of low complexity AAC (AAC-LC which is a part of MPEG2 part7 + PNS tool added) with spectral band replication (SBR) added to it for enhancing bandwidth extensions and parametric stereo (PS) used for coding at low bit-rates. It supports mono or 2-channel stereo signals. In case of AAC-LC mode, the codec operates on 16/24-bit PCM sampled at 8 – 96 KHz and generates bit-streams having a maximum bit-rate of 576 kbps. When SBR is enabled, the codec limits sampling frequency to 16 – 48 KHz and generates compressed bit-streams having a maximum bit-rate of 128 kbps. PS is used when the overall bit-rate is less than 44 kbps.  The codec is widely deployed in portable media players, mobile phones, and in network connected devices.

SALIENT FEATURES
  • Optimized ASM/C implementation.
  • Re-entrant implementation
  • C-callable APIs
  • Supports sampling frequencies ranging from 8 KHz to 96 KHz in AAC-LC mode, 32KHz to 48 KHz in SBR/PS mode.
  • Supports bitrate for AAC-LC – 8 kbps to 576 kbps per channel, AAC+(SBR) – 10kbps to 44kbps for mono and 18kbps to 52kbps for stereo, EAAC+(PS) – 10kbps to 44kbps.
  • Support for mono and 2-channel stereo Input.
  • Support for 16-bit PCM input.
  • Support for downmixing of input stereo signal.
  • Supports mono only encoding configuration at compile time.
  • Supports configuration of AAC-LC, SBR and PS at compilation time
  • Supports average bitrate, VBR is not supported.
  • Supports TNS, M/S stereo tools.
  • Supports ADIF, ADTS and RAW packing formats.
  • Support for little-endian implementation on ARM9E.
  • Optional support for packing in MP4/3gp container formats
  • Optional support for xDM APIs.
TESTING FEATURES
  • Implementation tested for audio quality for a wide range of standard and non-standard test vectors.
  • Evaluated objective audio quality based on ITU BS.1387 standard
  • Listening tests performed with few cases to ensure that no artifacts are present in encoded output
  • Tested for graceful exit in case of errors or exception
  • Tested for illegal memory access by the module on ARM platform.
  • Module is fully interruptible.
  • Tested for compliance with register preservation requirements
  • Tested for Input buffer corruption
  • Tested for I/O buffer alignment requirements
  • Tested for multi-instance implementation.
  • Tested with scratch contamination at frame boundaries
  • Tested for 100% code coverage
  • Tested for any align faults.
  • Range validation of all API parameters
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467/OMAPL138 (ARM926EJ-S) platforms.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, and Cortex-A9

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EAAC+ Decoder

AC-LC DECODER

CODEC OVERVIEW

AAC is one of the most efficient perceptual audio coding algorithms. AAC uses a modular approach in encoding providing the flexibility to use different tools depending on the application and complexity requirements. AAC offers different profiles by making use of tools such as TNS, PNS, Mid-Side stereo, Intensity stereo, and frequency domain prediction. TNS (Temporal Noise Shaping) tool minimizes the temporal spread of quantization error for transient signals, PNS (Perceptual Noise Substitution) tool controls quantization resolution by doing noise generation for few bands, and mid-side and intensity stereo tool exploits inter-channel redundancy. AAC-LC is a low complexity version of AAC, and does not support frequency domain prediction tool, it is standardized by MPEG-2 (part 7) and MPEG-4 (part 3). AAC-LC operates on frames of 1024 samples, which are sampled at 8-96 Khz and generates compressed bit-streams having bit-rates from 8 to 576 kbps per channel. AAC-LC is widely used in many audio applications and deployed in portable devices.

SALIENT FEATURES
  • Based on the 3GPP standard (3GPP TS 26.411 v7.3.0)
  • Optimized ASM/C implementation.
  • Re-entrant implementation
  • C-callable APIs
  • Supports sampling frequencies ranging from 8 KHz to 96 Khz.
  • Supports for 16-bit PCM output.
  • Supports bitrate from 8 kbps to 576 kbps per channel.
  • Support for mono and 2-channel stereo output.
  • Support for optional packet loss concealment, downmix, and resampler modules.
  • Supports ADIF, ADTS and RAW packing formats.
  • Support for little-endian implementation on ARM9E.
  • Supports interleaved and de-interleaved output.
  • Optional support for xDM APIs.
TESTING FEATURES
  • Implementation is tested for wide range of standard and non-standard test vectors.
  • Tested for graceful exit in case of bit-stream related errors or exception.
  • Tested for illegal memory access by the module on ARM platform.
  • Module is fully interruptible.
  • Tested for compliance with register preservation requirements
  • Tested for Input buffer corruption
  • Tested for I/O buffer alignment requirements
  • Tested for multi-instance implementation.
  • Tested with scratch contamination at frame boundaries
  • Tested for any align faults.
  • Tested for 100% code coverage
  • Range validation of all API parameters
  • Tested for packet loss concealment.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, and Cortex-A9

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AMR-WB+

AMR-WB+

CODEC OVERVIEW

Adaptive Multi Rate  Wideband Plus (AMR-WB+) codec was standardized by 3GPP in the year 2004. The codec operates on speech and audio signals sampled at 8 – 48 KHz and generates compressed bit-streams with bit-rates ranging from  6 to 36 kbps for mono and 8 to 48 kbps for stereo signals respectively. It uses a hybrid coding approach that combines the strength of speech and audio codecs. When compared with audio codecs, it performs better for speech and mixed (speech and audio) content type input signals. Internally, the codec operates at a nominal sampling frequency of 25.6 KHz. Gradual bit rate and bandwidth scaling is achieved by scaling the internal sampling frequency from 0.5 to 1.5 times the nominal sampling frequency. Correspondingly, it provides an audio bandwidth that ranges from 6.4 KHz (lowest bit-rate) to 19.2 KHz (highest bit-rate). The encoder has a low-complexity option for implementation on terminal devices and the decoder has an inherent packet loss concealment mechanism. The principal applications for this codec include low bit-rate multimedia services such as music, speech, news, sportscasts, weather, movies, audio books, training, person-to-person MMS, commercials etc. on mobile networks.

SALIENT FEATURES
  • Based on 3GPP specification.
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech and mixed (speech and audio) signals sampled at 8 – 48 KHz
  • Support for bitrates ranging from 6 36 kbps for mono and 8 48 kbps for stereo.
  • The bitrate can be configured at 20ms frame boundary.
  • Support for RAW, FSF, TIF, IF1, IF2, and MMS bit-stream formats.
  • Supports integrated Voice Activity Detection (VAD) algorithm.
  • Support for all modes and ISF defined in the standard.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Supports integrated Voice Activity Detection (VAD) algorithm.
  • Little-endian implementation on C64x+
  • Little- and big-endian implementation on ARM
  • Encoder optimized for low-complexity use case
  • Decoder supports llimiter flag for smoothing the output signal and avoid clipping.
  • Option to force output to mono
  • Option to specify the sampling frequency of the output PCM samples
  • Optional support for xDM APIs
TESTING FEATURES
  • Bit-exact with the standard test vectors.
  • Module is fully interruptible. Maximum interrupt latency on C64x+ is 6000 cycles.
  • Tested for any illegal memory access by the module (C64x+ and ARM).
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested for Packet loss conditions with 5% loss to 25% loss
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK and DM6446 EVM.
  • AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C64x+/C66x, and AMD/Intel 64-bit cores supporting SSE4 and above.

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AAC-LC Encoder

AAC-LC ENCODER

CODEC OVERVIEW

AAC is one of the most efficient perceptual audio coding algorithms. AAC uses a modular approach in encoding providing the flexibility to use different tools depending on the application and complexity requirements. AAC offers different profiles by making use of tools such as TNS, PNS, Mid-Side stereo, Intensity stereo, and frequency domain prediction. TNS (Temporal Noise Shaping) tool minimizes the temporal spread of quantization error for transient signals, PNS (Perceptual Noise Substitution) tool controls quantization resolution by doing noise generation for few bands, and mid-side and intensity stereo tool exploits inter-channel redundancy. AAC-LC is a low complexity version of AAC, and does not support frequency domain prediction tool, it is standardized by MPEG-2 (part 7) and MPEG-4 (part 3). AAC-LC operates on frames of 1024 samples, which are sampled at 8-96 Khz and generates compressed bit-streams having bit-rates from 8 to 576 kbps per channel. AAC-LC is widely used in many audio applications and deployed in portable devices

SALIENT FEATURES
  • Optimized ASM/C implementation.
  • Re-entrant implementation
  • C-callable APIs
  • Supports sampling frequencies ranging from 8 KHz to 96 Khz.
  • Supports bitrate from 8 kbps to 576 kbps per channel.
  • Support for mono and 2-channel stereo Input.
  • Support for 16-bit PCM input.
  • Support for downmixing of input stereo signal.
  • Supports mono only encoding configuration at compile time.
  • Supports average bitrate; VBR is not supported.
  • Supports TNS, M/S stereo tools.
  • Supports ADIF, ADTS and RAW packing formats.
  • Support for little-endian implementation on ARM9E.
  • Optional support for xDM APIs.
TESTING FEATURES
  • Implementation tested for audio quality for a wide range of standard and non-standard test vectors.
  • Evaluated objective audio quality based on ITU BS.1387 standard
  • Listening tests performed with few cases to ensure that no artifacts are present in encoded output
  • Tested for graceful exit in case of errors or exception
  • Tested for illegal memory access by the module on ARM platform.
  • Module is fully interruptible.
  • Tested for compliance with register preservation requirements
  • Tested for Input buffer corruption
  • Tested for I/O buffer alignment requirements
  • Tested for multi-instance implementation.
  • Tested with scratch contamination at frame boundaries
  • Tested for 100% code coverage
  • Tested for any align faults.
  • Range validation of all API parameters
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467/OMAPL138 (ARM926EJ-S) platforms.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, and Cortex-A9

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AAC-LC Decoder

AAC-LC DECODER

CODEC OVERVIEW

AAC is one of the most efficient perceptual audio coding algorithms. AAC uses a modular approach in encoding providing the flexibility to use different tools depending on the application and complexity requirements. AAC offers different profiles by making use of tools such as TNS, PNS, Mid-Side stereo, Intensity stereo, and frequency domain prediction. TNS (Temporal Noise Shaping) tool minimizes the temporal spread of quantization error for transient signals, PNS (Perceptual Noise Substitution) tool controls quantization resolution by doing noise generation for few bands, and mid-side and intensity stereo tool exploits inter-channel redundancy. AAC-LC is a low complexity version of AAC, and does not support frequency domain prediction tool, it is standardized by MPEG-2 (part 7) and MPEG-4 (part 3). AAC-LC operates on frames of 1024 samples, which are sampled at 8-96 Khz and generates compressed bit-streams having bit-rates from 8 to 576 kbps per channel. AAC-LC is widely used in many audio applications and deployed in portable devices.

SALIENT FEATURES
  • Based on the 3GPP standard (3GPP TS 26.411 v7.3.0)
  • Optimized ASM/C implementation.
  • Re-entrant implementation
  • C-callable APIs
  • Supports sampling frequencies ranging from 8 KHz to 96 Khz.
  • Supports for 16-bit PCM output.
  • Supports bitrate from 8 kbps to 576 kbps per channel.
  • Support for mono and 2-channel stereo output.
  • Support for optional packet loss concealment, downmix, and resampler modules.
  • Supports ADIF, ADTS and RAW packing formats.
  • Support for little-endian implementation on ARM9E.
  • Supports interleaved and de-interleaved output.
  • Optional support for xDM APIs.
TESTING FEATURES
  • Implementation is tested for wide range of standard and non-standard test vectors.
  • Tested for graceful exit in case of bit-stream related errors or exception.
  • Tested for illegal memory access by the module on ARM platform.
  • Module is fully interruptible.
  • Tested for compliance with register preservation requirements
  • Tested for Input buffer corruption
  • Tested for I/O buffer alignment requirements
  • Tested for multi-instance implementation.
  • Tested with scratch contamination at frame boundaries
  • Tested for any align faults.
  • Tested for 100% code coverage
  • Range validation of all API parameters
  • Tested for packet loss concealment.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, and Cortex-A9

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Acoustic Echo Canceller

ACOUSTIC ECHO CANCELLER

MODULE OVERVIEW

CouthIT’s acoustic echo cancellation implementation is designed to continuously and adaptively cancels the unwanted echo generated by the coupling between the loudspeaker and the microphone and maximize the user experience by providing high quality full duplex communication in all environments. The algorithm implemented is compatible with the ITU-T G.167 recommendation. The implementation is targeted for wide range of applications such as VoIP, tele-conferencing and loud speaking audio systems.

SALIENT FEATURES
  • Fixed-point ANSI C implementation.
  • Re-entrant implementation.
  • C-callable APIs
  • Module is fully interruptible.
  • Implementation independent of the sampling rate.
  • Operates on a 10ms frame size.
  • Fast Convergence rate (greater than 20dB/sec).
  • Automatically adapts to the real time echo path changes
  • User can configure to use either full duplex or near full duplex mode depending on hardware capability and requirement.
  • Robust novel double talk detector based on speech detectors and cross correlation statistics to prevent loss of convergence.
  • Fully compliant to ITU-T G.167 requirements.
  • User configurable echo tail length in a multiple of 10ms upto 120ms.
  • Protection against non linearity caused by low frequency components.
  • Provides more than 60dB of acoustic echo cancellation.
  • Howling control to eliminates acoustic howling / squealing interference.
  • Effective non linear processor to remove non-linear residual echo with smoothing.
  • High pass filter to remove non-linear low frequency components thereby improving the performance of AEC.
  • Insertion of comfort noise during silence periods to discontinuity in the speech signals.
  • Optimized for low memory foot print and low complexity.
  • Integrated with AGC to maintain dynamic range of the speech signal (optional).
  • Integrated with NS to remove residual echo and background noise (optional).
TESTING FEATURES
  • Tested using a large database of male and female speech test vectors.
  • Tested for full duplex operation and for divergence in double talk scenario.
  • Tested for removal of howling / squealing interference.
  • Tested for convergence in case of high level of background noise.
  • Tested for convergence in the presence of varying speech signal levels.
  • Tested in conjunction with CouthIT’s Noise suppression, AGC, jitter buffer and speech codec modules.
  • Tested for graceful exit in case of errors or exception.
  • Tested for Input buffer corruption
  • Tested for I/O buffer alignment requirements
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage
  • Range validation of all API parameters.
  • Code validated on ARM926EJ-S (OMAP L138) platform running Open Embedded Linux
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-A8, and Cortex-A9

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AMR-WB or G.722.2

AMR-WB or G.722.2

CODEC OVERVIEW

Adaptive Multi Rate – Wideband (AMR-WB) speech coding standard was developed by 3GPP in the year 2002. It has also been adopted by the ITU-T as the G.722.2 standard. The codec operates on speech signals sampled at 16 KHz and generates compressed bit-streams with bit-rates ranging from 6.6kbps to 23.85kbps. The bit-rate can be changed at 20 ms frame boundary. The coding scheme used for the various bit-rate modes is based on the Algebraic Code Excited Linear Prediction algorithm. It also has an integrated voice activity detector and packet loss concealment algorithm. The principal applications for this codec include wideband telephony applications over 3G wireless and VoIP such as audio teleconferencing, and streaming.

SALIENT FEATURES
  • Based on 3GPP specification.
  • Fixed-point ANSI C implementation on TI/ARM platform.
  • On AMD/Intel, Encoder is based on floating-point ANSI C implementation, and Decoder is based on fixed-point ANSI C implementation.
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signal sampled at 16 KHz.
  • Support for bitrates ranging from 6.6kbps to 23.85kbps.
  • The bitrate can be configured at 20ms frame boundary.
  • Support for RAW, IF1, IF2, and RFC bit-stream formats.
  • Supports integrated Voice Activity Detection (VAD) algorithm.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Optional support for xDM APIs
  • The implementation supports both Little-Endian and Big-Endian (on ARM and C64x+ platforms).
TESTING FEATURES
  • Fixed-point implementation is bit-exact with the standard test vectors.
  • Module is fully interruptible. Maximum interrupt latency on C64x+ is 6000 cycles.
  • Tested for any illegal memory access by the module (C64x+ and ARM).
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested for Packet loss conditions with 5% loss to 25% loss
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK and DM6446 EVM.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • Cortex-M4 implementation validated on the TI Tiva TM4C1294 EVM.
  • AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.
AVAILABLE PLATFORM(S)

ARM9E, ARM11, Cortex-M4, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.

For datasheet with resource usage details
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