G.722 speech codec was standardized by ITU-T in 1988. The encoder operates on 14-bit speech/audio signals sampled at 16 KHz and generates a compressed bit-stream having a bit rate of 64kbps. The codec transforms the speech/audio signals using the Sub-Band ADPCM (SB-ADPCM) algorithm. The application at the transmit side can truncate each octet generated by the encoder by 1 or 2 bits to insert auxiliary data before transmission. The codec therefore provides an auxiliary data channel rate of 0, 8 or 16 kbps respectively. Decoder can be operated in one of 3 modes corresponding to bitrates 64, 56 or 48 kbps respectively. Appendix IV of the standard specifies a low complexity PLC algorithm for the decoder. The target applications for this codec includes the fixed network Voice over IP applications.
- Based on ITU-T specification.
- Optimized ASM/C implementation.
- Re-entrant implementation.
- C-callable APIs.
- Operates on speech/audio signals sampled at 16 KHz.
- Configurable frame length (minimum size — 2 samples, default – 160 samples)
- Support for 48, 56, and 64 kbps bit-rates.
- Support for RTP payload format as specified in RFC 3551.
- Support for packet loss concealment as specified in Appendix IV of the Standard.
- Optional support for xDM APIs on TI platforms.
- Tested for bit-exactness with standard as well as a large database of non-standard test vectors.
- Module is fully interruptible.
- Tested for compliance with register preservation requirements.
- Tested for Input buffer corruption.
- Tested for I/O buffer alignment requirements.
- Tested for multi-instance implementation.
- Tested for 100% code coverage.
- Range validation for all the API parameters.
- Tested with scratch contamination at frame boundaries.
- Tested for packet loss conditions with 5% loss to 25% loss.
- TI C64x implementation validated on Spectrum Digital C6416 DSK.
- TI C64x+ implementation validated on Spectrum Digital C6455 DSK.
- ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
- AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.
ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, TI C66x, and AMD/Intel 64-bit cores supporting SSE4 and above.