Enhanced Voice Services (EVS) speech coding standard was developed by 3GPP in the year 2014. The codec operates on 20ms frames of 16-bit PCM speech/audio signals sampled at 8 KHz, 16 KHz, 32 KHz, or 48 KHz and generates a compressed bit-stream having bit-rates in the range of 5.9 kbps to 128 kbps respectively. EVS has been developed primarily for VoLTE and is inter-operable with the 3GPP AMR-WB codec. At 5.9 kbps, it operates in variable bit rate and it also has a robust channel aware mode at 13.2 kbps for lossy networks. All other bit-rates operate in constant bit-rate mode. Encoder uses the ACELP core for speech input, DTX mode for inactive input, and MDCT mode for audio input. The decoder supports packet loss concealment and has an inherent jitter buffer management for handling packet loss and delay jitter.
- Based on EVS standard Release 12.1
- Fixed-point ANSI C implementation on TI platform.
- Floating-point ANSI C implementation on AMD/Intel platform.
- Re-entrant implementation
- C-callable APIs
- Optimized C/Assembly implementation
- Operates on 20 ms frame length
- Operates on speech/audio signals sampled at 8 KHz, 16KHz, 32KHz, and 48 KHz
- Supports bit-rates ranging from 5.9 kbps to 128 kbps
- Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR) and channel aware modes
- Supports inter-operability with the 3GPP AMR-WB codec
- Supports configuring bandwidth at int- and run-time.
- Supports configuring the bit-rate at init- and run-time
- Supports Forward Error Correction (FEC) for good robustness
- Supports integrated Packet Loss Concealment (PLC) algorithm
- Supports VAD/DTX/CNG configurable at init- and run-time
- Optional support for xDM APIs on TI platform
- Fixed-point implementation is tested for bit-exactness with standard as well as a large database of non-standard test vectors.
- Module is fully interruptible.
- C64x+/C66x implementations tested for any illegal memory access.
- Tested for compliance with register preservation requirements
- Tested for Input buffer corruption
- Tested for I/O buffer alignment requirements
- Tested for multi-instance implementation
- Tested for 100% code coverage
- Range validation for all the API parameters
- Tested with scratch contamination at frame boundaries
- Tested for packet loss conditions with 5% loss to 25% loss
- C64x+ implementation validated on C6472EVM platform.
- C66x implementation validated on C6678EVM platform.
- AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.
TI C66x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.