Adaptive Multi Rate – Wideband (AMR-WB) speech coding standard was developed by 3GPP in the year 2002. It has also been adopted by the ITU-T as the G.722.2 standard. The codec operates on speech signals sampled at 16 KHz and generates compressed bit-streams with bit-rates ranging from 6.6kbps to 23.85kbps. The bit-rate can be changed at 20 ms frame boundary. The coding scheme used for the various bit-rate modes is based on the Algebraic Code Excited Linear Prediction algorithm. It also has an integrated voice activity detector and packet loss concealment algorithm. The principal applications for this codec include wideband telephony applications over 3G wireless and VoIP such as audio teleconferencing, and streaming.
- Based on 3GPP specification.
- Fixed-point ANSI C implementation on TI/ARM platform.
- On AMD/Intel, Encoder is based on floating-point ANSI C implementation, and Decoder is based on fixed-point ANSI C implementation.
- Optimized ASM/C implementation.
- Re-entrant implementation.
- C-callable APIs.
- Operates on speech signal sampled at 16 KHz.
- Support for bitrates ranging from 6.6kbps to 23.85kbps.
- The bitrate can be configured at 20ms frame boundary.
- Support for RAW, IF1, IF2, and RFC bit-stream formats.
- Supports integrated Voice Activity Detection (VAD) algorithm.
- Supports integrated Packet Loss Concealment (PLC) algorithm.
- Optional support for xDM APIs
- The implementation supports both Little-Endian and Big-Endian (on ARM and C64x+ platforms).
- Fixed-point implementation is bit-exact with the standard test vectors.
- Module is fully interruptible. Maximum interrupt latency on C64x+ is 6000 cycles.
- Tested for any illegal memory access by the module (C64x+ and ARM).
- Tested for compliance with register preservation requirements.
- Tested for Input buffer corruption.
- Tested for I/O buffer alignment requirements.
- Tested for multi-instance implementation.
- Tested for 100% code coverage.
- Range validation for all the API parameters.
- Tested for Packet loss conditions with 5% loss to 25% loss
- ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
- TI C64x+ implementation validated on Spectrum Digital C6455 DSK and DM6446 EVM.
- TI C55x implementation validated on Spectrum Digital C5510 DSK.
- Cortex-M4 implementation validated on the TI Tiva TM4C1294 EVM.
- AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.
ARM9E, ARM11, Cortex-M4, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.