GSM Half Rate (GSM-HR) speech codec was developed in the 1990s and was adopted by the 3GPP for mobile telephony. The codec operates on each 20 ms frame of speech signals sampled at 8 KHz and generates compressed bit-streams with an average bit-rate of 5.6 kbps. The codec uses Vector Sum Excited Linear Prediction coder (VSELP) technique to compress speech. The codec provides voice activity detection (VAD) and comfort noise generation (CNG) algorithms and an inherent packet loss concealment (PLC) algorithm for handling frame erasures. The codec was primarily developed for mobile telephony over GSM networks.
- Based on 3GPP specification.
- Optimized C implementation.
- Re-entrant implementation.
- C-callable APIs.
- Operates on speech signal sampled at 8 KHz.
- Support for bit rate 5.6 kbps.
- Supports integrated Packet Loss Concealment (PLC) algorithm.
- The codec supports integrated Voice Activity Detection (VAD) algorithm configurable at init-time.
- Optional support for xDM APIs.
- The implementation supports both Little-Endian and Big-Endian versions.
- Tested for bit exactness with the standard as well as large database of non-standard test vectors.
- Module is fully interruptible. Maximum interrupt latency on C64x+ is 6000 cycles.
- Tested for any illegal memory access by the module.
- Tested for compliance with register preservation requirements.
- Tested for Input buffer corruption.
- Tested for I/O buffer alignment requirements.
- Tested for multi-instance implementation.
- Tested for 100% code coverage.
- Range validation for all the API parameters.
- Tested for Packet loss conditions with 5% loss to 25% loss.
- TI C64x+ implementation validated on Spectrum Digital C6455 DSK.
- ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platform.
- AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.
ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C64x+, TI C66x, and AMD/Intel 64-bit cores supporting SSE4 and above.