AMR-WB+

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AMR-WB+

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Codec overview

Adaptive Multi Rate Wideband Plus (AMR-WB+) codec was standardized by 3GPP in the year 2004. The codec operates on speech and audio signals sampled at 8 - 48 KHz and generates compressed bit-streams with bit-rates ranging from 6 to 36 kbps for mono and 8 to 48 kbps for stereo signals respectively. It uses a hybrid coding approach that combines the strength of speech and audio codecs. When compared with audio codecs, it performs better for speech and mixed (speech and audio) content type input signals. Internally, the codec operates at a nominal sampling frequency of 25.6 KHz. Gradual bit rate and bandwidth scaling is achieved by scaling the internal sampling frequency from 0.5 to 1.5 times the nominal sampling frequency. Correspondingly, it provides an audio bandwidth that ranges from 6.4 KHz (lowest bit-rate) to 19.2 KHz (highest bit-rate). The encoder has a low-complexity option for implementation on terminal devices and the decoder has an inherent packet loss concealment mechanism. The principal applications for this codec include low bit-rate multimedia services such as music, speech, news, sportscasts, weather, movies, audio books, training, person-to-person MMS, commercials etc. on mobile networks.

Salient features

  • Based on 3GPP specification.
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech and mixed (speech and audio) signals sampled at 8 - 48 KHz
  • Support for bitrates ranging from 6 36 kbps for mono and 8 48 kbps for stereo.
  • The bitrate can be configured at 20ms frame boundary.
  • Support for RAW, FSF, TIF, IF1, IF2, and MMS bit-stream formats.
  • Supports integrated Voice Activity Detection (VAD) algorithm.
  • Support for all modes and ISF defined in the standard.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Supports integrated Voice Activity Detection (VAD) algorithm.
  • Little-endian implementation on C64x+
  • Little- and big-endian implementation on ARM
  • Encoder optimized for low-complexity use case
  • Decoder supports llimiter flag for smoothing the output signal and avoid clipping.
  • Option to force output to mono
  • Option to specify the sampling frequency of the output PCM samples
  • Optional support for xDM APIs

Testing features

  • Bit-exact with the standard test vectors.
  • Module is fully interruptible. Maximum interrupt latency on C64x+ is 6000 cycles.
  • Tested for any illegal memory access by the module (C64x+ and ARM).
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested for Packet loss conditions with 5% loss to 25% loss
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK and DM6446 EVM.

Available Platform(s)

ARM9E, ARM11, Cortex-A8, Cortex-A9, and TI C64x+.

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